library ieee;
use ieee.std_logic_1164.all;

entity mplex2x1 is
port(a,b,s:in std_logic;
	f:out std_logic);
	
end mplex2x1;


architecture bhv of mplex2x1 is
begin

f<= a when s='0' else
	b when s='1' else
	'-';

end bhv;